1. Field of Invention
This invention relates to integrated circuit packages, and more particularly to the disassembly of a flip chip integrated circuit package for subsequent evaluation.
2. Description of Related Art
During manufacture of an integrated circuit (e.g., a microprocessor), signal lines formed upon the silicon substrate which are to be connected to external devices are terminated at flat metal contact regions called input/output (I/O) pads. Following manufacture, the integrated circuit (i.e., chip) is typically secured within a protective semiconductor device package. Each I/O pad of the integrated circuit is then connected to one or more terminals of the device package. The terminals of a device package are typically arranged about the periphery of the package. Fine metal wires are typically used to connect the I/O pads of the integrated circuit to the terminals of the device package. Some types of device packages have terminals called "pins" for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called "leads" for attachment to flat metal contact regions on an exposed surface of a PCB. Newer ball grid array ("BGA") device packages described below have solder balls for attachment to flat metal pads on an exposed surface of a PCB.
As integrated circuit fabrication technology improves, manufacturers are able to integrate more and more functions onto single silicon substrates. As the number of functions on a single integrated circuit increases, the number of signal lines which need to be connected to external devices also increase. The corresponding number of required I/O pads and device package terminals increase as well, as do the complexities and costs of the device packages. Constraints of high-volume PCB assembly operations place lower limits on the physical dimensions of device packages and distances between device package terminals. As a result, the areas of peripheral-terminal device packages having hundreds of terminals are largely proportional to the number of terminals. In addition, the lengths of signal lines from integrated circuit I/O pads to device package terminals increase with the number of terminals, and the high-frequency electrical performance of larger peripheral-terminal device packages suffer as a result.
Controlled collapse chip connection (C4) is a well known method of attaching an integrated circuit directly to a substrate made of, for example, fiberglass-epoxy printed circuit board material or a ceramic material (e.g., aluminum oxide, alumina, Al.sub.2 O.sub.3, or aluminum nitride, AlN). The C4 attachment method is commonly referred to as the "flip chip" method. In preparation for C4 attachment, the I/O pads of the integrated circuit are typically arranged in a two-dimensional array upon an underside surface of the integrated circuit, and a corresponding set of bonding pads are formed upon an upper surface of the substrate. A solder "bump" is formed upon each of the I/O pads of the integrated circuit. During C4 attachment of the integrated circuit to the substrate, the solder bumps are placed in physical contact with the bonding pads of the substrate. The solder bumps are then heated long enough for the solder to reflow. When the solder cools, the I/O pads of the integrated circuit are electrically and mechanically coupled to the bonding pads of the substrate. After the integrated circuit is attached to the substrate, the region between the integrated circuit and the substrate is filled with an "underfill" material which encapsulates the C4 connections and provides other mechanical advantages.
Grid array semiconductor device packages have terminals arranged in a two-dimensional array across the underside surface of the device package. As a result, the physical dimensions of grid array device packages having hundreds of terminals are much smaller than their peripheral-terminal counterparts. Such smaller packages are highly desirable in portable device applications such as laptop and palmtop computers and hand-held communications devices such as cellular telephones. In addition, the lengths of signal lines from integrated circuit I/O pads to device package terminals are shorter, thus the high-frequency electrical performances of grid array device packages are typically better than those of corresponding peripheral-terminal device packages. Grid array device packages also allow the continued use of existing PCB assembly equipment developed for peripheral-terminal devices.
An increasingly popular type of grid array device package is the ball grid array (BGA) device package. FIG. 1 is a cross-sectional view of one embodiment of a BGA device package 10 in current use. BGA device 10 includes an integrated circuit 12 mounted upon an upper surface of a larger package substrate 14. Substrate 14 may be made of, for example, fiberglass-epoxy printed circuit board material or a ceramic material (e.g., aluminum oxide or aluminum nitride). Substrate 14 includes two sets of bonding pads: a first set adjacent to integrated circuit 12 and a second set arranged in a two-dimensional array across the underside surface of device package 10. The I/O pads of integrated circuit 12 are connected to corresponding members of the first set of bonding pads using the C4 technique described above. Members of the second set of bonding pads function as device package terminals, and have solder balls 15 attached to the bonding pads. Solder balls 15 allow device package 10 to be surface mounted to an ordinary PCB.
Substrate 14 includes one or more layers of electrically conductive "traces" (i.e., signal lines) which connect respective members of the first and second sets of bonding pads. In the embodiment of FIG. 1, a conductive trace 16 formed upon the upper surface of substrate 14 connects a member of the first set of bonding pads 18 to a corresponding member of the second set of bonding pads 20 by way of a vertical via 22. A layer of a solder mask material 24 forms a dielectric layer over conductive trace 16, and also seals and protects conductive trace 16 from moisture and reactive gases in the ambient.
Prior to C4 mounting of integrated circuit 12 upon substrate 14, a stiffener 26 is attached to the perimeter of the upper surface of substrate 14 by a first adhesive layer 28. Stiffener 26 helps substrate 14 maintain a substantially planar shape during and after C4 mounting of integrated circuit 12 upon substrate 14. The material used to form first adhesive layer 28 is typically a thermosetting polymer (e.g., an epoxy resin) which is dispensed in liquid form and becomes substantially rigid (i.e., hardens) during a curing process (e.g., with time and/or elevated temperature). First adhesive layer 28 may be, for example, a layer of an epoxy compound including particles of a thermally conductive material (e.g., silver, aluminum, boron nitride, etc.).
During the C4 mounting of integrated circuit 12 upon substrate 14, solder bumps 30 are heated long enough for the solder to reflow. When the solder cools, the I/O pads are electrically and mechanically coupled to corresponding members of the first set of bonding pads. A layer of underfill material 32 is then formed in the region between integrated circuit 12 and substrate 14.
Following the C4 mounting process, a heat spreader 34 is attached to the upper surface of stiffener 26. Heat spreader 34 conducts heat energy away from integrated circuit 12 during operation. During the attachment process, a thermal interface layer 36 is formed between heat spreader 34 and integrated circuit 12, and a second adhesive layer 38 is formed between heat spreader 34 and stiffener 26. Thermal interface layer 36 may be, for example, a layer of a an epoxy compound including particles of a thermally conductive material (e.g., silver, aluminum, boron nitride, etc.). Alternately, thermal interface layer 36 may be a layer of thermal grease, thermal wax, or a piece of thermal interface tape. Second adhesive layer 38 may be, for example, a layer of an epoxy compound including particles of a thermally conductive material (e.g., silver, aluminum, boron nitride, etc.).
Device packages must routinely be disassembled in order to evaluate the fabrication process and for failure analysis. To separate stiffener 26 and substrate 14, a thin wedge (e.g., a razor blade) is typically forced into first adhesive layer 28 between stiffener 26 and substrate 14. The wedge cuts through a portion of first adhesive layer 28. The wedge may also be used to pry stiffener 26 and substrate 14 apart, breaking an uncut portion of first adhesive layer 28. Prior to the separation process, first adhesive layer 28 may be softened by heating device package 10.
The above described process is used to expose integrated circuit 12 and substrate 14 for examination. Separating stiffener 26 and substrate 14 so as to gain access to integrated circuit 12 and substrate 14 often results in damage to substrate 14. For example, layer of solder mask material 24 and underlying conductive traces (e.g., conductive trace 16) formed upon the upper surface of substrate 14 are typically scratched or broken during the process, making subsequent electrical evaluation of substrate 14 difficult or impossible.
It would be beneficial to have an apparatus and method for separating a stiffener member from a substrate of a flip chip integrated circuit package such that the substrate is not damaged. Such an apparatus and method would facilitate subsequent substrate examination for evaluation of a fabrication process used to form the device, or for failure analysis.